In general, as semiconductor memory devices are scaled in increasingly greater capacity and integration, the number of memory cells included in one chip increases progressively. To effectively control a read/write operation for the memory cells, a certain number of cells are bundled to form a cell matrix, and a number of cell matrices are bundled to form a bank. A bit line and a word line are used for approaching each of a plurality of cells included in a cell matrix.
For dynamic random access memories (DRAMs), which are a type of nonvolatile memory, each of the cells may be configured with one transistor and one capacitor. The word line is generally connected to a gate of the transistor, and the bit line is generally connected to a drain of the transistor. To perform a read/write operation for data stored in one cell, when a word line corresponding to the cell is activated, the transistor forms a channel, and an electric charge stored in the capacitor is transferred to the bit line through the channel. The electric charge transferred to the bit line is weak in intensity, and thus a bit line sense amplifier is used to amplify the electric charge in order for an accurate read/write operation to be performed.
FIG. 1 illustrates a circuit diagram of a conventional sense amplifier circuit for a nonvolatile memory.
As illustrated in FIG. 1, the conventional sense amplifier circuit includes a first PMOS transistor PM11, a second PMOS transistor PM12, a first NMOS transistor NM11, and a second NMOS transistor NM12.
The first PMOS transistor PM11 has a source connected to a source voltage VDD terminal, a bulk connected to the source voltage VDD terminal, a gate connected to a sensing enable node SAENb to which a sensing enable signal is applied, and a drain connected to a bit line node BL to which a bit line signal is applied.
The second PMOS transistor PM12 has a source connected to the source voltage VDD, a bulk connected to the source voltage VDD, a gate connected to a bit line node BL, and a drain connected to a sense amplifier based logic (SABL) node.
The first NMOS transistor NM11 has a source connected to a ground voltage VSS, a bulk connected to the ground voltage VSS, a gate connected to the sensing enable node SAENb, and a drain connected to the bit line node BL.
The second NMOS transistor NM12 has a source connected to the ground voltage VSS, a bulk connected to the ground voltage VSS, a gate connected to the bit line node BL, and a drain connected to the SABL node.
The conventional sense amplifier circuit further includes an inverter INV0 that is connected between the SABL node and a data output terminal DATA. The inverter INV0 logically inverts a signal applied to the SABL node to output the inverted signal on the data output terminal DATA.
The operation of the conventional sense amplifier circuit having the above-described configuration will now be described.
First, when not sensing a memory cell, the sensing enable signal having a logic high is inputted to the sensing enable node SAENb.
The voltage VDD having a logic high is inputted to the gate of the first PMOS transistor PM11 to turn off the first PMOS transistor PM11.
The voltage VDD having a logic high is inputted to the gate of the first NMOS transistor NM11 to turn on the first NMOS transistor NM11, and thus, the ground voltage VSS is outputted on the bit line node BL.
The ground voltage VSS having a logic low is inputted to the gate of the second NMOS transistor NM12 to turn off the second NMOS transistor NM12.
The ground voltage VSS having a logic low is inputted to the gate of the second PMOS transistor PM12 to turn on the second PMOS transistor PM12, and thus the source voltage VDD having a logic high is applied to the SABL node.
The source voltage VDD having a logic high is applied to the SABL node, and thus, 0 V (zero volt) corresponding to a logic low is outputted on the data output terminal DATA. Consequently, a current may not flow in a selected memory cell coupled to the bit line when the ground voltage VSS is applied to the source of the memory cell, and if any current does flow in the selected memory cell, it is sunk by the first NMOS transistor NM11.
However, when an active sensing enable signal (e.g., having a logic low) is inputted to the sensing enable node SAENb, the selected memory cell coupled to the bit line is sensed.
The ground voltage VSS having a logic low is inputted to the gate of the first PMOS transistor PM11 to turn on the first PMOS transistor PM11, and thus the source voltage having a logic high is applied on the bit line node BL. The ground voltage VSS having a logic low is also inputted to the gate of the first NMOS transistor NM11 to turn off the first NMOS transistor NM11.
The source voltage VDD having a logic high is inputted to the gate of the second NMOS transistor NM12 to turn on the second NMOS transistor NM12, and thus the ground voltage VSS having a logic low is applied to the SABL node. The source voltage VDD having a logic high is also inputted to the gate of the second PMOS transistor PM12 to turn off the second PMOS transistor PM12.
The ground voltage VSS having a logic low is applied to the SABL node, and thus, the source voltage VDD having a logic high is outputted on the data output terminal DATA.
When a current does not flow in the selected memory cell, the source voltage VDD having a logic high is outputted on the data output terminal DATA.
Moreover, when current does not flow in the memory cells coupled to the bit line, and a ground voltage VSS is applied to the sources of the memory cells, the active sensing enable signal inputted as a logic low to the sensing enable node SAENb for sensing the memory cell may not have a desired effect.
For example, the ground voltage VSS having a logic low is inputted to the gate of the first PMOS transistor PM11 to turn on the first PMOS transistor PM11, and thus, the source voltage VDD is applied to the bit line node BL. However, since current does not flow in the memory cells, the electric potential of the bit line node BL remains at an electric potential of a logic low.
The ground voltage VSS having a logic low is also inputted to the gate of the first NMOS transistor NM11 to turn off the first NMOS transistor NM11.
A logic low is further inputted to the gate of the second NMOS transistor NM12 to turn off the second NMOS transistor NM12.
A logic low is also inputted to the gate of the second PMOS transistor PM12 to turn on the second PMOS transistor PM12, and thus, the source voltage VDD having a logic high is applied to the SABL node.
The source voltage VDD having a logic high is applied to the SABL node, and thus, the ground voltage VSS having a logic low is outputted on the data output terminal DATA.
When current does not flow in the memory cells coupled to the bit line, the ground voltage VSS having a logic low is outputted on the data output terminal DATA.
In the conventional sense amplifier circuit for a nonvolatile memory, however, the sense amplifier circuit operates when the ground voltage VSS is applied to the source of a memory cell, and particularly, as the amount of a current flowing in the memory cell becomes lower, the length-direction size of the first PMOS transistor PM11 is enlarged. For this reason, a current capable of sensing is limited.